Application specific integrated circuits (ASIC) allow a designer to implement exactly the intellectual property blocks (also referred to as IP or macro function blocks) and/or memories needed, in the quantities needed, for a particular design. However, a structured ASIC can provide less design flexibility because much of the IP, particularly memories, is fixed within the base slice of the structured ASIC. Utilizing the fixed memories in ways to satisfy the designer specification, when the memory type is not an exact match has been a focus of product development. Much of the development has focused on joining memories to form different sizes, or splitting a single physical dual port memory into two logical single port memories.
One memory configuration not addressed by previous solutions is a memory with a high port count, such as a 3 or 4 port memory. There is not necessarily a requirement for high bandwidth access to memory on each of the ports in many architectures, but rather each port may need to support a different clock domain (not necessarily a different clock frequency on each port). However, high port count memories tend to be less die efficient and are less desirable to implement in a structured ASIC. Also, there is less of a consensus for the requirements for high port count memories among designers, making the high port count memories less amenable to diffusion onto structured ASICs. Thus, it is economically undesirable to build structured ASICs with high port count memories, yet designers can need such memories.
One current solution for the problem is to have a designer re-architect the design requirements. However, re-architecting the problem to reduce clock domains is not always feasible. The clock domains are frequently outside the control of the chip design and the system box design. Rather, the clock domains are in the realm of the network design.
Another solution uses another memory block to implement a first-in first-out (FIFO) memory on one or more of the ports. Adding a FIFO memory to a port to reduce the clock domains presented to the main memory (or buffer memory) is the most common solution. However, the FIFO memory uses another memory block to implement, and again, memory blocks are a finite, limited resource on a structured ASIC. In addition, even if the FIFO size requirement is quite small, the memory blocks available on the structured ASIC can be much larger than necessary, and are seldom physically located nearby on the die. Thus, the use of the limited memory resource can be somewhat inefficient and can require more routing that can potentially impact performance. The primary problem is when a designer has to utilize multiple physical memories for FIFOs to implement multiport/clock domain memories, yet also needs most/all the memory blocks for other parts of the design.
It would be desirable to have an efficient implementation of multiple clock domain accesses to diffused memories in structured application specific integrated circuits (structured ASICs).